Half Adder Gate level
module ha2(input a, input b, output sum , output carry);
xor a1(s,a,b);
and a2(c ,a ,b );
endmodule
//testbench for half adder
module stimulus;
reg a,b;
wire s,c;
ha2 uut(a,b,s,c);
initial
begin
a=0 ; b=0;
#10 a=0 ; b=1;
#10 a=1;b=0;
#10 a=1;b=1;
end
endmodule
Full Adder Gate Level
FULLmodule Gfulladder(input a, input b,input c, output sum, output carry);
wire s1,s2,s3,s4;
xor a1(s1, a, b);
xor a3(sum, s1, c);
xor a4(s2, a, b);
xor a5(s3, b, c);
xor a6(s4, a, c);
xor a7(carry,s2,s3,s4);
endmodule
4:1 MUX (GATE LEVEL)
module mux4_1_gatelevel(input i0, inputi1, inputi2, inputi3, input s1,input s0,output out);
wire s1n,s0n;
wire y0,y1,y2,y3;
not(s1n,s1);
not(s0n,s0);
and(y0,i0,s1n,s0n);
and(y1,i1,s1n,s0);
and(y2,i2,s1,s0n);
and(y3,i3,s1,s0);
or(out,y0,y1,y2,y3);
Decoder 2 to 4 (GATE LEVEL)
module GDECODER(input a, input b, output d0,d1,d2,d3);
wire s1,s2;
not n1(s1,a);
not n2(s2,b);
and a1(d0,s1,s2);
and a2(d1,s1,b);
and a3(d2,a,s2);
and a1(d3,a,b);
endodule
Jk ff async reset
Module jk_ff(j,k,clk,rst,q);
input J,K,CLK,RST;
outputreg q = 1’b0;
always@(posedgeclk or posedgerst)
begin
if(rst)
q<=1’b0;
else
case({j,k})
0: q<=q;
1: q<=1’b0;
2:q<=1’b1;
3:q<=~q;
Endcase
End
Endmodule
D type positive edge triggered
Ff with async reset
module_ff(d, rst, clk , q,qb);
input d,rst,clk;
oupu regq,qb;
always@(posedgeclk or negedgerst)
begin
if(!rst)
begin
q=0; qb =1;
end else
begin
q =d;
qb =~d;
end
end
endmodule
4 bit bcd counter with sync reset
Modulehbcd(clk,rst,q);
Input clk , rst ;
Output reg[3:0] q;
Always@(posedgeclk)
Begin
If(rst| q>= 9)
Q<=4’d0;
Else
Q<=q+1;
End endmodule