4 to 1 MUX


    library ieee;
    use ieee.std_logic_1164.all;
    entity mux_4to1 is
    port( A,B,C,D : in bit;
        S1,S0: in bit;
        Y: out bit);
    end mux_4to1;
    architecture bhv of mux_4to1 is
    begin
      process (A,B,C,D,S0,S1) is
        begin
          if (S1 ='0' and S0 = '0') then
              Y<= A;
          elsif (S1 ='0' and S0 = '1') then
              Y<= B;
          elsif (S1 ='1' and S0 = '0') then
              Y<= C;
          else
              Y<= D;
        end if;
      end process;
    end bhv;

1 to 4 DEMUX


    library ieee;
    use ieee.std_logic_1164.all;
    entity demux_1to4 is
        port(F : in bit;
        S0,S1: in bit;
        A,B,C,D: out bit);
    end demux_1to4;
    architecture bhv of demux_1to4 is
    begin
      process (F,S0,S1) is
        begin
          if (S1 ='0' and S0 = '0') then
            A <= F;
          elsif (S1 ='0' and S0 = '1') then
            B <= F;
          elsif (S1 ='1' and S1 = '0') then
            C <= F;
          else
            D <= F;
          end if;
      end process;
    end bhv;