JK flip-flop


library ieee;
use ieee. std_logic_1164.all;
entity JK_FF is
    port( J,K,CLOCK: in std_logic;
        Q, Qb: out std_logic);
end JK_FF;	
architecture behavioral of JK_FF is
begin
    process(CLOCK)
    variable TMP: std_logic;
    begin
        if(rising_edge(CLOCK)) then
            if(J='0' and K='0')then
                TMP:=TMP;
            elsif(J='1' and K='1')then
                TMP:= not TMP;
            elsif(J='0' and K='1')then
                TMP:='0';
            else
                TMP:='1';
            end if;
        end if;
        Q <= TMP;
        Qb <= not TMP;
    end PROCESS;
end behavioral;

D flip-flop


library ieee;
use ieee. std_logic_1164.all;

entity D_FF is
    PORT( D,CLOCK: in std_logic;
        Q,Qb: out std_logic);
end D_FF;	
 
architecture behavioral of D_FF is
begin
    process(CLOCK)
    variable TMP: std_logic;
    begin
        if(rising_edge(CLOCK)) then
            TMP :=D;
        end if;
        Q <= TMP;
        Qb<=not TMP;
    end process;
end behavioral;